One common type of integrated circuit is a memory circuit having a plurality of memory cells arranged in a two-dimensional array. In order to facilitate access to the memory cells, a plurality of conductive runs known as bitlines extend in a direction from one end of the array to the other end, with each memory cell being electrically coupled to two of the bitlines. When information is read from or written into one of the memory cells, the two bitlines coupled to that cell carry a differential voltage. Most such memory circuits read and write information to or from several memory cells at the same time, for example where each such cell corresponds to a respective bit of a binary word. Thus, at a given point in time, each of the bitlines in the memory circuit may be carrying one side of a respective differential signal associated with a respective memory cell.
For a number of years, there have been ongoing efforts to decrease the physical size of these memory circuits within an integrated circuit. As a result, the physical size of these memory circuits has progressively decreased over time, such that a given amount of memory storage has been implemented in progressively smaller and smaller amounts of the area of a semiconductor wafer. Consequently, over time, the bitlines associated with a memory cell array have necessarily moved closer and closer to each other, which in turn has tended to increase the capacitive coupling between the bitlines.
Capacitive coupling is most acute in a form of these memory circuits where each column of memory cells is served by a single pair of bitlines which, throughout their length, extend parallel to each other and also parallel to bitlines in adjacent columns. In order to reduce capacitive coupling between a bitline in one column with respect to a bitline in an adjacent column, a known technique is to provide the two bitlines in each column with several twists or crossovers at spaced locations along their lengths, with the crossovers in each pair of adjacent columns being staggered or offset. Another known technique is different, in that it does not use a single pair of bitlines to serve an entire column of memory cells. Instead, each bitline is routed in a stairstep manner across other bitlines until an outer side of the memory circuit is reached, and then is routed back across the other bitlines in a stairstep manner.
In all of these known techniques, virtually all the material of the bitlines is in a single metalization layer. In the approaches where a bitline crosses another bitline, one of the bitlines will have, in a second metalization layer, a very short portion which is just long enough to effect the crossover. While these known techniques have been generally adequate for their intended purposes, they have not been satisfactory in all respects.
More specifically, as advances in fabrication techniques have permitted the size of these types of memory circuits to be progressively reduced, the bitlines have moved progressively closer to each other, such that capacitive coupling remains a progressively increasing problem, even where two given bitlines are adjacent each other over a relatively short portion of their length. New techniques are needed to deal with the progressively increasing levels of capacitive coupling that result from advances in fabrication technology.